A DRAM (Dynamic Random Access Memory) is widely used as an information storage device that serves as a main memory for a personal computer or like system. Among others, an SDRAM (Synchronous Dynamic Random Access Memory or Synchronous DRAM), which is faster than a previously used, asynchronous DRAM, has been increasingly used. The SDRAM is a memory device that synchronizes its operation with a base clock frequency. Timing recognition is properly accomplished because it is in synchronism with a clock signal. Due to such timing recognition, the SDRAM operates rapidly. The SDRAM can transmit data with high efficiency particularly in a situation where data is continuously output in synchronism with a system clock (e.g., burst transfer).
The operation of the SDRAM will now be described. Within a single clock, an activate operation, read or write operation, precharge operation, and other operations are used for data handling. These operations are designated by a command from a memory controller or other external device. Basic operations will now be outlined. The activate operation is performed to acquire memory cell data by amplifying it with a sense amplifier. The read operation is performed to output the data existing in the sense amplifier via an output buffer. The write operation is performed to deliver the data in an I/O line to the sense amplifier. The precharge operation is performed to write the data existing in the sense amplifier back into a memory cell.
A known technology of synchronous semiconductor storage device is disclosed, for instance, by Japanese Patent Laid-open No. 2002-074953 reduces the current consumption by activating an input buffer circuit on a necessary operating cycle only without impairing an input buffer's rapid response.
In general, a conventional SDRAM is designed to perform an activate operation, read or write operation, or precharge operation within a single clock. A common SDRAM is limited in terms of time for operation assurance. Further, latency and real-time limitations are imposed on command issuance. The latency is limited without regard to the synchronizing clock frequency. A typical latency is a CAS latency, which denotes the number of clocks required for the interval between the instant at which a read command is issued and the instant at which data is output. On the other hand, the real-time limitations are generally related, for instance, to a Tras (RAS activate time) parameter, which represents the time between an activate operation and precharge operation, a Trcd (RAS-CAS delay time) parameter, which represents the time between an activate operation and read operation, and Trp (precharge time) parameter, which represents the time between a precharge operation and activate operation. Command issuance needs to be performed after a wait of at least the above-mentioned time. If a command is issued without such a wait, the operation is not guaranteed.
When the operating frequency is decreased so that the clock period is longer than the aforementioned real-time limit, which is one of the time limitations on the SDRAM, the command issue timing is determined for each cycle. Therefore, even if a command can be issued on each clock, most of the clock period is vacant and unnecessary for operations. As a result, the performance of the SDRAM deteriorates.
Further, as an example of an SDRAM, one known DRAM simultaneously performs an activate operation, read or write operation, and precharge operation like an SRAM (Static Random Access Memory). This type of DRAM is at an advantage in that a DRAM controller does not have to exercise page management. However, a precharge operation is performed on every clock. Therefore, the power consumption is not low although the common DRAM features low power consumption.
The present invention has been made in view of the above technical circumstances, and provides an information storage device and information storage method for exercising a synchronous information storage device function for controlling the operation timing with a synchronizing clock signal, performing a highly efficient operation process to provide improved performance, and assures low power consumption, which is peculiar to DRAMs.